Multi-function interface and applications thereof

ABSTRACT

A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1 st  type of input signal when the interface is in a 1 st  mode and operably coupled to pass a 2 nd  type of input signal when the interface is in a 2 nd  mode. The configurable driver module is operably coupled to amplify the 1 st  type of input signal when the interface is in the 1 st  mode and to amplify the 2 nd  type of input signal when the interface is in the 2 nd  mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1 st  output impedance of the interface when the interface is in the 1 st  mode and to provide a 2 nd  output impedance when the interface is in the 2 nd  mode.

This patent application is claiming priority under 35 USC § 119(e) toprovisional patent application having the same title as the presentapplication, a provisional Ser. No. of 60/419,044, and a provisionalfiling date of Oct. 16, 2002.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates generally to data communications and moreparticularly to high-speed wired data communications.

2. Description of Related Art

As is known, communication technologies that link electronic devices aremany and varied, servicing communications via both physical media andwirelessly. Some communication technologies interface a pair of devices,other communication technologies interface small groups of devices, andstill other communication technologies interface large groups ofdevices.

Examples of communication technologies that couple small groups ofdevices include buses within digital computers, e.g., PCI (peripheralcomponent interface) bus, ISA (industry standard architecture) bus, anUSB (universal serial bus), SPI (system packet interface) among others.One relatively new communication technology for coupling relativelysmall groups of devices is the HyperTransport (HT) technology,previously known as the Lightning Data Transport (LDT) technology(HyperTransport I/O Link Specification “HT Standard”). The HT Standardsets forth definitions for a high-speed, low-latency protocol that caninterface with today's buses like AGP, PCI, SPI, 1394, USB 2.0, and 1Gbit Ethernet as well as next generation buses including AGP 8×,Infiniband, PCI-X, PCI 3.0, and 10 Gbit Ethernet. HT interconnectsprovide high-speed data links between coupled devices. Most HT enableddevices include at least a pair of HT ports so that HT enabled devicesmay be daisy-chained. In an HT chain or fabric, each coupled device maycommunicate with each other coupled device using appropriate addressingand control. Examples of devices that may be HT chained include packetdata routers, server computers, data storage devices, and other computerperipheral devices, among others.

Of these devices that may be HT chained together, many requiresignificant processing capability and significant memory capacity. Thus,these devices typically include multiple processors and have a largeamount of memory. While a device or group of devices having a largeamount of memory and significant processing resources may be capable ofperforming a large number of tasks, significant operational difficultiesexist in coordinating the operation of multiple processors. While eachprocessor may be capable of executing a large number operations in agiven time period, the operation of the processors must be coordinatedand memory must be managed to assure coherency of cached copies. In atypical multi-processor installation, each processor typically includesa Level 1 (L1) cache coupled to a group of processors via a processorbus. The processor bus is most likely contained upon a printed circuitboard. A Level 2 (L2) cache and a memory controller (that also couplesto memory) also typically couples to the processor bus. Thus, each ofthe processors has access to the shared L2 cache and the memorycontroller and can snoop the processor bus for its cache coherencypurposes. This multi-processor installation (node) is generally acceptedand functions well in many environments.

However, network switches and web servers often times require moreprocessing and storage capacity than can be provided by a single smallgroup of processors sharing a processor bus. Thus, in someinstallations, a plurality processor/memory groups (nodes) is sometimescontained in a single device. In these instances, the nodes may be rackmounted and may be coupled via a back plane of the rack. Unfortunately,while the sharing of memory by processors within a single node is afairly straightforward task, the sharing of memory between nodes is adaunting task. Memory accesses between nodes are slow and severelydegrade the performance of the installation. Many other shortcomings inthe operation of multiple node systems also exist. These shortcomingsrelate to cache coherency operations, interrupt service operations, etc.

While HT links provide high-speed connectivity for the above-mentioneddevices and in other applications, they are inherently inefficient insome ways. For example, in a “legal” HT chain, one HT enabled deviceserves as a host bridge while other HT enabled devices serve as duallink tunnels and a single HT enabled device sits at the end of the HTchain and serves as an end-of-chain device (also referred to as an HT“cave”). According to the HT Standard, all communications must flowthrough the host bridge, even if the communication is between twoadjacent devices in the HT chain. Thus, if an end-of-chain HT devicedesires to communicate with an adjacent HT tunnel, its transmittedcommunications flow first upstream to the host bridge and then flowdownstream from the host bridge to the adjacent destination device. Suchcommunication routing, while allowing the HT chain to be well managed,reduces the overall throughput achievable by the HT chain.

Applications, including the above-mentioned devices, that otherwisebenefit from the speed advantages of the HT chain are hampered by theinherent delays and transaction routing limitations of current HT chainoperations. Because all transactions are serviced by the host bridge andthe host a limited number of transactions it can process at a giventime, transaction latency is a significant issue for devices on the HTchain, particularly so for those devices residing at the far end of theHT chain, i.e., at or near the end-of-chain device. Further, because allcommunications serviced by the HT chain, both upstream and downstream,must share the bandwidth provided by the HT chain, the HT chain may haveinsufficient total capacity to simultaneously service all requiredtransactions at their required bandwidth(s). Moreover, a limited numberof transactions may be addressed at any time by any one device such asthe host, e.g., 32 transactions (2**5). The host bridge is thereforelimited in the number of transactions that it may have outstanding atany time and the host bridge may be unable to service all requiredtransactions satisfactorily. Each of these operational limitationsaffects the ability of an HT chain to service the communicationsrequirements of coupled devices.

Further, even if an HT enabled device were incorporated into a system(e.g., an HT enabled server, router, etc. were incorporated into ancircuit-switched system or packet-switched system), it would be requiredto interface with a legacy device that uses an older communicationprotocol. For example, if a line card were developed with HT ports, theline card would need to communicate with legacy line cards that includeSPI ports.

Therefore, a need exists for methods and/or apparatuses for interfacingdevices using one or more communication protocols in one or moreconfigurations while overcoming the bandwidth limitations, latencylimitations, and other limitations associated with the use of ahigh-speed HT chain.

BRIEF SUMMARY OF THE INVENTION

The multi-function interface of the present invention substantiallymeets these needs and others. The embodiment of the multi-functioninterface includes a digital interface module, a configurable drivermodule, and a configurable output impedance module. The digitalinterface module is operably coupled to pass a 1^(st) type of inputsignal (e.g., one formatted in accordance with HyperTransport protocol)when the interface is in a 1^(st) mode and operably coupled to pass a2^(nd) type of input signal (e.g., one formatted in accordance withsystem packet interface protocol) when the interface is in a 2^(nd)mode. The configurable driver module is operably coupled to amplify the1^(st) type of input signal when the interface is in the 1^(st) mode andto amplify the 2^(nd) type of input signal when the interface is in the2nd mode. The configurable output impedance module is coupled to theconfigurable driver module to provide a 1^(st) output impedance of theinterface when the interface is in the 1^(st) mode and to provide a2^(nd) output impedance when the interface is in the 2nd mode.Accordingly, when the multi-function interface is incorporated in amultiprocessor device, the multiprocessor device may be configured in aplurality of ways using one or more communication protocols to overcomebandwidth limitations, latency limitations and other limitationsassociated with the use of high speed HyperTransport chains.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a processing system in accordancewith the present invention;

FIG. 2 is a schematic block diagram of an alternate processing system inaccordance with the present invention;

FIG. 3 is a schematic block diagram of another processing system inaccordance with the present invention;

FIG. 4 is a schematic block diagram of a multiple processor device inaccordance with the present invention;

FIG. 5 is a graphical representation of transporting data betweendevices in accordance with the present invention;

FIG. 6 is a schematic block diagram of a multi-function interface thatmay be used as a transmitter input/output module in accordance with thepresent invention;

FIG. 7 is a schematic block diagram of an alternate multi-functioninterface that may be used as a transmitter input/output module inaccordance with the present invention;

FIG. 8 is a schematic block diagram of a differential multi-functioninterface that may be used as a transmit input/output module inaccordance with the present invention;

FIG. 9 is a schematic block diagram of the interface module of FIG. 8functioning in accordance with a 1^(st) mode of operation in accordancewith the present invention; and

FIG. 10 is a schematic block diagram of the multi-function interface ofFIG. 8 configured in accordance with a 2^(nd) mode of operation inaccordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of a processing system 10 thatincludes a plurality of multiple processor devices A-G. Each of themultiple processor devices A-G include at least two interfaces, which inthis illustration are labeled as T for tunnel functionality or H forhost or bridge functionality. The details of the multiple processordevices A-G will be described in greater detail with reference to FIG.4.

In this example of a processing system 10, multiple processor device Dis functioning as a host to support two primary chains. The 1^(st)primary chain includes multiple processor device C, which is configuredto provide a tunnel function, and multiple processor device B, which isconfigured to provide a bridge function. The other primary chainsupported by device D includes multiple processor devices E, F, and G,which are each configured to provide tunneling functionality. Theprocessing system 10 also includes a secondary chain that includesmultiple processor devices A and B. where device A is configured toprovide a tunneling function. Multiple processor device B functions asthe host for the secondary chain. By convention, data from the devices(i.e., nodes) in a chain to the host device is referred to as downstreamdata and data from the host device to the node devices is referred to asupstream data.

In general, when a multiple processor device is providing a tunnelingfunction, it passes, without interpretation, all packets received fromdownstream devices (i.e., the multiple processor devices that, in thechain, are further away from the host device) to the next upstreamdevice (i.e., an adjacent multiple processor device that, in the chain,is closer to the host device). For example, multiple processor device Eprovides all downstream packets received from downstream multipleprocessor devices F and G to host device D without interpretation, evenif the packets are addressing multiple processor device F or G. The hostdevice modifies the downstream packets to identify itself as the sourceof downstream packets and sends the modified packets upstream along withany packets that it generated. As the multiple processor devices receivethe upstream packets, they interpret the packet to identify the hostdevice as the source and to identify a destination. If the multipleprocessor device is not the destination, it passes the upstream packetsto the next downstream node. For example, packets received from the hostdevice D that are directed to the multiple processor device E will beprocessed by the multiple processor device E, but device E will passpackets for devices F and G. The processing of packets by device Eincludes routing the packets to a particular processing unit withindevice E, routing to local memory, routing to external memory associatedwith device E, et cetera.

In this configuration, if multiple processor device G desires to sendpackets to multiple processor device F, the packets would traversethrough devices E and F to host device D. Host device D modifies thepackets identifying the multiple processor device D as the source of thepackets and provide the modified packets to multiple processor device E,which would in turn forward them to multiple processor device F. Asimilar type of processing occurs between multiple processor device Band multiple processor device C, between devices G and E, and betweendevices E and F.

For the secondary chain, devices A and B can communication directly,i.e., they support peer-to-peer communications therebetween. In thisinstance, the multiple processor device B has one of its interfaces (H)configured to provide a bridge function. According, the bridgefunctioning interface of device B interprets packets it receives fromdevice A to determine the destination of the packet. If the destinationis local to device B (i.e., meaning the destination of the packet is oneof the modules within multiple processor device B or associated withmultiple processor device B), the H interface processes the receivedpacket. The processing includes forwarding the packet to the appropriatedestination within, or associated with, device B.

If the packet is not destined for a module within device B, multipleprocessor device B modifies the packet to identify itself as the sourceof the packets. The modified packets are then forwarded to the hostdevice D via device C, which is providing a tunneling function. Forexample, if device A desires communication with device C, device Aprovides packets to device B and device B modifies the packets toidentify device B as the source of the packets. Device B then providesthe modified packets to host device D via device C. Host device D then,in turn, modifies the packets to identify itself as the sources of thepackets and provides the again modified packets to device C, where thepackets are subsequently processed. Conversely, if device C were totransmit packets to device A, the packets would first be sent to host D,modified by device D, and the modified packets would be provided back todevice C. Device C, in accordance with the tunneling function, passesthe packets to device B. Device B interprets the packets, identifiesdevice A as the destination, and modifies the packets to identify deviceB as the source. Device B then provides the modified packets to device Afor processing thereby.

In the processing system 10, device D, as the host, assigns a node ID(identification code) to each of the other multiple processor devices inthe system. Multiple processor device D then maps the node ID to a unitID for each device in the system, including its own node ID to its ownunit ID. Accordingly, by including a bridging functionality in device B,in accordance with the present invention, the processing system 10allows for interfacing between devices using one or more communicationprotocols and may be configured in one or more configurations whileovercoming bandwidth limitations, latency limitations and otherlimitations associated with the use of high speed HyperTransport chains.

As one of average skill in the art will appreciate, the particularprotocol for data transmission between devices may be in accordance witha HyperTransport protocol, system packet interface (SPI) protocol and/orother types of packet-switched or circuit-switched protocols.

FIG. 2 is a schematic block diagram of an alternate processing system 20that includes a plurality of multiple processor devices A-G. In thissystem 20, multiple processor device D is the host device while theremaining devices are configured to support a tunnel-bridge hybridinterfacing functionality. Each of multiple processor devices A-C andE-G have their interfaces configured to support the tunnel-bridge hybrid(H/T) mode. With the interfacing configured in this manner, peer-to-peercommunications may occur between multiple processor devices in a chain.For example, multiple processor device A may communicate directly withmultiple processor device B and may communicate with multiple processordevice C, via device B, without routing packets through the host deviceD. For peer-to-peer communication between devices A and B, multipleprocessor device B interprets the packets received from multipleprocessor device A to determine whether the destination of the packet islocal to multiple processor device B. With reference to FIG. 4, adestination associated with multiple processor device B may be anyone ofthe processing units 42-44, cache memory 46 or system memory accessiblethrough the memory controller 48. Returning back to the diagram of FIG.2, if the packets received from device A are destined for a modulewithin device B, device B processes the packets by forwarding them tothe appropriate module within device B. If the packets are not destinedfor device B, device B forwards them, without modifying the source ofthe packets, to multiple processor device C.

The packets received by multiple processor device C are interpreted todetermine whether a module within multiple processor device C is thedestination of the packets. If so, device C processes them by forwardingthe packets to the appropriate module within, or associated with, deviceC. If the packets are not destined for a module within device C, deviceC forwards them to the multiple processor device D. Device D modifiesthe packets to identify itself as the source of the packets and providesthe modified packets to the chain including devices E-G. Devices E-G, inorder, interpret the modified packets to determine whether it is adestination of the modified packets. If so, the device processes thepackets. If not, the device routes the packets to the next device inchain. In addition, devices E-G support peer-to-peer communications in asimilar manner as devices A-C. Accordingly, by configuring theinterfaces of the devices to support a tunnel-bridge hybrid function,the source of the packets is not modified (except when thecommunications are between primary chains of the system), which enablesthe devices to use one or more communication protocols (e.g.,HyperTransport, system packet interface, et cetera) in a peer-to-peerconfiguration that substantially overcomes the bandwidth limitations,latency limitations and other limitations associated with the use of aconventional high-speed HyperTransport chain.

FIG. 3 is a schematic block diagram of processing system 30 thatincludes multiple processor devices A-G. In this embodiment, multipleprocessor device D is functioning as a host device for the system whilethe remaining multiple processor devices A-C and E-G are configured tosupport a bridge functionality. In this configuration, each of thedevices may communicate directly (i.e., have peer-to-peer communication)with adjacent multiple processor devices via cascaded secondary chains.For example, device A may directly communicate with device B via asecondary chain therebetween, device B with device C via a secondarychain therebetween, device E with device F via a secondary chaintherebetween, and device F with device G via a secondary chaintherebetween. The primary chains in this example of a processing systemexist between device D and device C and between device D and device E.

For communication between devices A and B, device B interprets packetsreceived from device A to determine their destination. If device B isthe destination, it processes it by providing it to the appropriatedestination within, or associated with, device B. If the packet is notdestined for device B, device B modifies the packet to identify device Bas the source and forwards it to device C. Accordingly, if device Adesires to communicate with device B, it does so via device B. However,for device A to communicate with device C, device B, as the host for thechain between devices A and B, modifies the packets to identify itselfas the source of the packets. The modified packets are then routed todevice C. To device C, the packets appear to be coming from device B andnot device A. For packets from device C to device A, device B modifiesthe packets to identify itself as the source of the packets and providesthe modified packets to device A. In such a configuration, each deviceonly knows that it is communicating with one device in the downstreamdirect and one device in the upstream direction. As such, peer-to-peercommunication is supported directly between adjacent devices and is alsosupported indirectly (i.e., by modifying the packets to identify thehost of the secondary chain as the source of the packets) between anydevices in the system.

In any of the processing systems illustrated in FIGS. 1-3, the deviceson one chain may communicate with devices on the other chain. An exampleof this is illustrated in FIG. 3 where device G may communicate withdevice C. As shown, packets from device G are propagated through devicesD, E and F until they reach device C. Similarly, packets from device Care propagated through devices D, E and F until they reach device G. Inthe example of FIG. 3, the packets in the downstream direction and inthe upstream direction are adjusted to modify the source of the packets.Accordingly, packets received from device G appear, to device C, to beoriginated by device D. Similarly, packets from device C appear, todevice G, to be sourced by device F. As one of average skill in the artwill appreciate, each devices that is providing a host function or abridge function maintains a table of communications for the chains it isthe host to track the true source of the packets and the truedestination of the packets.

FIG. 4 is a schematic block diagram of a multiple processor device 40 inaccordance with the present invention. The multiple processor device 40may be an integrated circuit or it may be comprised of discretecomponents. In either implementation, the multiple processor device 40may be used as multiple processor device A-G in the processing systemsillustrated in FIGS. 1-3.

The multiple processor device 40 includes a plurality of processingunits 42-44, cache memory 46, memory controller 48, which interfaceswith on and/or off-chip system memory, an internal bus 48, a nodecontroller 50, a switching module 51, a packet manager 52, and aplurality of configurable packet based interfaces 54-56 (only twoshown). The processing units 42-44, which may be two or more in numbers,may have a MIPS based architecture, to support floating point processingand branch prediction. In addition, each processing unit 42, 44 mayinclude a memory sub-system of an instruction cache and a data cache andmay support separately, or in combination, one or more processingfunctions. With respect to the processing system of FIGS. 1-3, eachprocessing unit 42 or 44 may be a destination within multiple processordevice 40 and/or each processing function executed by the processingmodules 42-44 may be a destination within the processor device 40.

The internal bus 48, which may be a 256 bit cache line wide splittransaction cache coherent orientated bus, couples the processing units42-44, cache memory 46, memory controller 48, node controller 50 andpacket manager 52 together. The cache memory 46 may function as an L2cache for the processing units 42-44, node controller 50 and/or packetmanager 52. With respect to the processing system of FIGS. 1-3, thecache memory 46 may be a destination within multiple processor device40.

The memory controller 48 provides an interface to system memory, which,when the multiple processor device 40 is an integrated circuit, may beoff-chip and/or on-chip. With respect to the processing system of FIGS.1-3, the system memory may be a destination within the multipleprocessor device 40 and/or memory locations within the system memory maybe individual destinations within the device 40. Accordingly, the systemmemory may include one or more destinations for the processing systemsillustrated in FIGS. 1-3.

The node controller 50 functions as a bridge between the internal bus 48and the configurable packet-based interfaces 54-56. Accordingly,accesses originated on either side of the node controller will betranslated and sent on to the other. The node controller also supportsthe distributed shared memory model associated with the cache coherencynon-uniform memory access (CC-NUMA) protocol.

The switching module 51 couples the plurality of configurablepacket-based interfaces 54-56 to the node controller 50 and/or to thepacket manager 52. The switching module 51 functions to direct datatraffic, which may be in a generic format, between the node controller50 and the configurable packet-based interfaces 54-56 and between thepacket manager 52 and the configurable packet-based interfaces 54. Thegeneric format may include 8 byte data words or 16 byte data wordsformatted in accordance with a proprietary protocol, in accordance withasynchronous transfer mode (ATM) cells, in accordance internet protocol(IP) packets, in accordance with transmission control protocol/internetprotocol (TCP/IP) packets, and/or in general, in accordance with anypacket-switched protocol or circuit-switched protocol.

The packet manager 52 may be a direct memory access (DMA) engine thatwrites packets received from the switching module 51 into input queuesof the system memory and reads packets from output queues of the systemmemory to the appropriate configurable packet-based interface 54-56. Thepacket manager 52 may include an input packet manager and an outputpacket manager each having its own DMA engine and associated cachememory. The cache memory may be arranged as first in first out (FIFO)buffers that respectively support the input queues and output queues.

The configurable packet-based interfaces 54-56 generally function toconvert data from a high-speed communication protocol (e.g., HT, SPI,etc.) utilized between multiple processor devices 40 and the genericformat of data within the multiple processor devices 40. Accordingly,the configurable packet-based interface 54 or 56 may convert received HTor SPI packets into the generic format packets or data words forprocessing within the multiple processor device 40. In addition, theconfigurable packet-based interfaces 54 and/or 56 may convert thegeneric formatted data received from the switching module 51 into HTpackets or SPI packets. The particular conversion of packets to genericformatted data performed by the configurable packet-based interfaces 54and 56 is based on configuration information 74, which, for example,indicates configuration for HT to generic format conversion or SPI togeneric format conversion.

Each of the configurable packet-based interfaces 54-56 includes a mediaaccess controller (MAC) 58 or 68, a receiver MAC 60 or 66, a transmitterinput/output module 62 or 72, and a receiver input/output module 64 or70. In general, the transmit MAC module 58 or 68 functions to convertoutbound data of a plurality of virtual channels in the generic formatto a stream of data in the specific high-speed communication protocol(e.g., HT, SPI, etc.) format. The transmit I/O module 62 or 72 generallyfunctions to drive the high-speed formatted stream of data onto thephysical link coupling the present multiple processor device 40 toanother multiple processor device. The transmit I/O module 62 or 72 isfurther described with reference to FIGS. 6-10. The receive MAC module60 or 66 generally functions to convert the received stream of data fromthe specific high-speed communication protocol (e.g., HT, SPI, etc.)format into data from a plurality of virtual channels having the genericformat. The receive I/O module 64 or 70 generally functions to amplifyand time align the high-speed formatted steam of data received via thephysical link coupling the present multiple processor device 40 toanother multiple processor device. The receive I/O module 64 or 70 isfurther described, and incorporated herein by reference, in co-pendingpatent application entitled RECEIVER MULTI-PROTOCOL INTERFACE ANDAPPLICATIONS THEREOF, having an attorney docket number of BP 2389.1, andhaving the same filing date and priority date as the presentapplication.

The transmit and/or receive MACs 58, 60, 66 and/or 68 may include,individually or in combination, a processing module and associatedmemory to perform its correspond functions. The processing module may bea single processing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on operationalinstructions. The memory may be a single memory device or a plurality ofmemory devices. Such a memory device may be a read-only memory, randomaccess memory, volatile memory, non-volatile memory, static memory,dynamic memory, flash memory, and/or any device that stores digitalinformation. Note that when the processing module implements one or moreof its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory storing the correspondingoperational instructions is embedded with the circuitry comprising thestate machine, analog circuitry, digital circuitry, and/or logiccircuitry. The memory stores, and the processing module executes,operational instructions corresponding to the functionality performed bythe transmitter MAC 58 or 68 as disclosed, and incorporated herein byreference, in co-pending patent application entitled TRANSMITTING DATAFROM A PLURALITY OF VIRTUAL CHANNELS VIA A MULTIPLE PROCESSOR DEVICE,having an attorney docket number of BP 2184.1 and having the same filingdate and priority date as the present patent application andcorresponding to the functionality performed by the receiver MAC module60 or 66 as disclosed, and incorporated herein by reference, inco-pending patent application entitled PROCESSING OF RECEIVED DATAWITHIN A MULTIPLE PROCESSOR DEVICE, having an attorney docket number ofBP 2184, and having the same filing date and priority date as thepresent patent application.

In operation, the configurable packet-based interfaces 54-56 provide themeans for communicating with other multiple processor devices 40 in aprocessing system such as the ones illustrated in FIGS. 1, 2 or 3. Thecommunication between multiple processor devices 40 via the configurablepacket-based interfaces 54 and 56 is formatted in accordance with aparticular high-speed communication protocol (e.g., HyperTransport (HT)or system packet interface (SPI)). The configurable packet-basedinterfaces 54-56 may be configured to support, at a given time, one ormore of the particular high-speed communication protocols. In addition,the configurable packet-based interfaces 54-56 may be configured tosupport the multiple processor device 40 in providing a tunnel function,a bridge function, or a tunnel-bridge hybrid function.

When the multiple processor device 40 is configured to function as atunnel-hybrid node, the configurable packet-based interface 54 or 56receives the high-speed communication protocol formatted stream of dataand separates, via the MAC module 60 or 68, the stream of incoming datainto generic formatted data associated with one or more of a plurality aparticular virtual channels. The particular virtual channel may beassociated with a local module of the multiple processor device 40(e.g., one or more of the processing units 42-44, the cache memory 46and/or memory controller 48) and, accordingly, corresponds to adestination of the multiple processor device 40 or the particularvirtual channel may be for forwarding packets to the another multipleprocessor device.

The interface 54 or 56 provides the generically formatted data words,which may comprise a packet or portion thereof, to the switching module51, which routes the generically formatted data words to the packetmanager 52 and/or to node controller 50. The node controller 50, thepacket manager 52 and/or one or more processing units 42-44 interpretsthe generically formatted data words to determine a destinationtherefor. If the destination is local to multiple processor device 40(i.e., the data is for one of processing units 42-44, cache memory 46 ormemory controller 48), the node controller 50 and/or packet manager 52provides the data, in a packet format, to the appropriate destination.If the data is not addressing a local destination, the packet manager52, node controller 50 and/or processing unit 42-44 causes the switchingmodule 51 to provide the packet to one of the other configurablepacket-based interfaces 54 or 56 for forwarding to another multipleprocessor device in the processing system. For example, if the data werereceived via configuration packet-based interface 54, the switchingmodule 51 would provide the outgoing data to configurable packet-basedinterface 56. In addition, the switching module 51 provides outgoingpackets generated by the local modules of processing module device 40 toone or more of the configurable packet-based interfaces 54-56.

The configurable packet-based interface 54 or 56 receives the genericformatted data via the transmitter MAC module 58 or 68. The transmitterMAC module 58, or 68 converts the generic formatted data from aplurality of virtual channels into a single stream of data. Thetransmitter input/output module 62 or 72 drives the stream of data on tothe physical link coupling the present multiple processor device toanother.

When the multiple processor device 40 is configured to function as atunnel node, the data received by the configurable packet-basedinterfaces 54 from a downstream node is routed to the switching module51 and then subsequently routed to another one of the configurablepacket-based interfaces for transmission downstream withoutinterpretation. For upstream transmissions, the data is interpreted todetermine whether the destination of the data is local. If not, the datais routed upstream via one of the configurable packet-based interfaces54 or 56.

When the multiple processor device 40 is configured as a bridge node,downstream packets that are received via a configurable packet-basedinterface 54 are modified via the packet manager 52, the node controller54 and/or processing units 42-44 to identify the current multipleprocessor device 40 as the source of the data. Having modified thesource, the switching module 51 provides the modified data to one of theconfigurable packet-based interfaces for transmission downstream. Forupstream transmissions, the multiple processor device 40 interprets thedata to determine whether it contains the destination for the data. Ifso, the data is routed to the appropriate destination. If not, themultiple processor device 40 forwards the packet via one of theconfigurable packet-based interfaces 54 or 56 to a downstream device.

To determine the destination of the data, the node controller 50, thepacket manager 52 and/or one of the processing units 42 or 44 interpretsheader information of the data to identify the destination. In addition,a set of ordering rules of the received data is applied when processingthe data, where processing includes forwarding the data, in packets, tothe appropriate local destination or forwarding it onto another device.The ordering rules include the ordering rules as defined in the HTspecification as well as non-posted commands are issued in order ofreception. The rules further include that the interfaces are aware ofwhether they are configured to support a tunnel, bridge, ortunnel-bridge hybrid node. With such awareness, for every ordered pairof transactions, the receiver portion of the interface will not make anew ordered pair visible to the switching module until the old orderedpair has been sent to the switching module. The node controller, inaddition to adhering to the HT specified ordering rules, treats all HTtransactions as being part of the same input/output stream, regardlessof which interface the transactions was received from. Accordingly, byapplying the appropriate ordering rules, the routing to and from theappropriate destinations either locally or remotely is accuratelyachieved.

FIG. 5 is a graphical representation of the functionality performed by acombination of the node controller 50, the switching module 51, thepacket manager 52 and/or the configurable packet-based interfaces 54 and56. In this illustration, data is transmitted over a physical linkbetween two devices in accordance with a particular high-speedcommunication protocol (e.g., HT, SPI-4, etc.). Accordingly, thephysical link supports a protocol that includes a plurality of packets.Each packet includes a data payload and a control section. The controlsection may include header information regarding the payload, controldata for processing the corresponding payload, and/or control data forsystem administration functions.

Within a multiple processor device, a plurality of virtual channels maybe established. A virtual channel may correspond to a particularphysical entity, such as processing units 42, 44, cache memory 46 and/ormemory controller 48, and/or to a logical entity such as a particularalgorithm being executed by processing module 42 or 44, particularmemory locations within cache memory 46 and/or particular memorylocations within system memory accessible via the memory controller 48.In addition, one or more virtual channels may correspond to data packetsreceived from downstream or upstream nodes that require forwarding.Accordingly, each multiple processor device supports a plurality ofvirtual channels. The data of the virtual channels, which is illustratedas data virtual channel number 1 (VC#1), virtual channel number 2 (VC#2)through virtual channel number N (VC#n) may have a generic format. Thegeneric format may be 8 byte data words, 16 byte data words thatcorrespond to a proprietary protocol, ATM cells, IP packets, TCP/IPpackets, other packet switched protocols and/or circuit switchedprotocols.

As illustrated, a plurality of virtual channels is sharing the physicallink between the two devices. The multiple processor device 40, via oneof the processing units 42-44, node controller 50 and/or packet manager52 manages the allocation of the physical link among the plurality ofvirtual channels. As shown, the payload of a particular packet may beloaded with a segment of a virtual channel. In this illustration, the1^(st) packet includes a segment, or fragment, of virtual channel number1. The data payload of the next packet receives a segment, or fragment,of virtual channel number 2. The allocation of virtual channels topackets may be done in a round-robin fashion, a weighted round-robinfashion or some other application of fairness to access the physicallink. The data transmitted across the physical link may be in a serialformat and at extremely high data rates (e.g., 3.125 gigabits-per-secondor greater).

At the receiving device, the serial stream of data is received and thenseparated into the corresponding virtual channels via the configurablepacket-based interface, the switching module 51, the node controller 50and/or packet manager 52. The recaptured virtual channel data is eitherprovided to an input queue for a local destination or provided to anoutput queue for forwarding via one of the configurable packet-basedinterfaces to another device. Accordingly, each of the devices in aprocessing system as illustrated in FIGS. 1-3 may utilize a high speedserial interface, or plurality of high speed serial interfaces, totransceive data from a plurality of virtual channels utilizing one ormore communication protocols and be configured in one or moreconfigurations while substantially overcoming the bandwidth limitations,latency limitations and other limitations associated with the use of ahigh speed HyperTransport chain. Configuring the multiple processordevices for application in the multiple configurations of processingsystems is described in greater detail and incorporated herein byreference in co-pending patent application entitled MULTIPLE PROCESSORINTEGRATED CIRCUIT HAVING CONFIGURABLE PACKET-BASED INTERFACES, havingan attorney docket number of BP 2186, and having the same filing dateand priority date as the present patent application.

FIG. 6 is a schematic block diagram of a multi-function interface thatmay be used as the transmit IO module 62 and/or 72 of the multiprocessordevice 40. The interface includes a digital interface module 80, aconfigurable driver 82 and a configurable output impedance 84. Thedigital interface module 80 is operably coupled to receive an inputsignal 86 from an associated transmitter MAC module 58 or 68. Thedigital interface module 80 will allow a 1^(st) type of input signal 86to pass when the configuration information 74 indicates a 1^(st) mode ofoperation to produce a passed input signal 88. The digital interfacemodule 80 will pass a 2^(nd) type of input signal 86 when theconfiguration information indicates a 2^(nd) mode of operation. Forexample, the 1^(st) mode of operation may be in accordance with a systempacket interface (SPI) protocol and the 2^(nd) mode may be in accordancewith a HyperTransport (HT) protocol. In general, the digital interfacemodule 80 determines a digital value of a control signal, which may beincluded in configuration information 74. When the control signal has a1^(st) digital value (e.g., corresponding to the 1^(st) mode ofoperation), the digital interface module 80 will pass a 1^(st) type ofinput signal. Conversely, when the control signal has a 2^(nd) digitalvalue (e.g., corresponding to the 2^(nd) mode of operation), the digitalinterface module 80 passes a 2^(nd) type of input signal.

The configurable driver 82 receives the passed input signal 88 andamplifies it in accordance with the 1^(st) or 2^(nd) mode of operationto produce an amplified input signal 90. The amplified input signal 90will be driven on the physical link coupling the present multiprocessordevice to another. In general, the configurable driver, when in the1^(st) mode, may be configured as a current steering driver to producethe amplified input signal 90 from the passed input signal 88 and havinga specific output impedance based on the corresponding configuration ofthe configurable output impedance 84. Alternatively, the configurabledriver 82 may be configured as a Class A or Class AB amplifier having asecond specific output impedance based on the correspondingconfiguration of the configurable output impedance 84 when the interfaceis in the 2^(nd) mode of operation to produce the amplified input signal90.

FIG. 7 is a schematic block diagram of a single-ended embodiment of thetransmit input/output modules 62 and/or 72 in accordance with thepresent invention. In this embodiment, the interface module includes thedigital interface module 80, the configurable driver 82 and theconfigurable output impedance 84. The digital interface module 80includes a pair of NAND gates, a pair of NOR gates, and a pair ofinverters. The configurable output impedance 84 includes an impedanceladder that has a 1^(st) end, a 2^(nd) end and a tap. In this example,the impedance ladder includes two resistors coupled in series, but maybe any passive or active component combination to provide a desiredoutput impedance for a given frequency range of operation. The remainingcomponents correspond to the configurable driver 82. To activate the1^(st) or 2^(nd) mode, the desired mode would be selected via a logic 1signal. As one of average skill in the art will appreciate, theconfiguration of the digital interface module 80 may be configured toactivate the particular mode on a logic low signal. When the 1^(st) modeis activated, (e.g., by a logic 1 signal) the 2^(nd) mode will bedeactivated via a logic low signal. The corresponding digital logiccircuitry for the 1^(st) mode includes NAND gate 1, NOR gate 2 and aninverter, which, in the first mode, allow the input signal 86 to pass totransistors T1 and T2 of the configurable driver. The digital logiccircuitry for the 2^(nd) mode of operation, NAND gate 2, NOR gate 1 andan inverter are held inactive such that the input signal 86 is notpassed to transistors T3 and T4 of the configurable driver.

With the mode 1 input high, the output of NAND gate corresponds to theinverse of input signal 86. Similarly, the output of NOR gate 2corresponds to the inverse of input signal 86. As such, when mode 1 isactivated, the amplified input signal 90 is produced via the switchingof transistors T1 and T2 and sourced by current sources I1 and I2. Theoutput impedance 84 is biased via a bias voltage coupled via transistorT5. Accordingly, in this mode, the I/O module 62 and/or 72 is providinga current steering function to produce the amplified input signal 90.

When mode 2 is enabled, (e.g., via a logic 1 signal) and mode 1 isdisabled (e.g., via a logic 0 signal), transistors T1, T2 and T5 areoff. Conversely, the digital interface module 80 passes the input signalto transistors T3 and T4. Transistors T3 and T4 in combination with theimpedance ladder provides the amplified input signal 90 from the inputsignal 86.

FIG. 8 is a schematic block diagram of a differential signalingembodiment of the transmitter input/output modules 62 and/or 72. In thisembodiment, the digital interface module 82 includes a plurality oflogic circuits that comprise NAND gates, NOR gates and inverters. Theconfigurable output impedance 84 includes two resistive ladders and theremaining components comprise the configurable driver 82. The operationof this embodiment will be described with reference to FIGS. 9 and 10.

FIG. 9 illustrates the transmitter input/output module 82 and/or 72 ofFIG. 8 configured in the 1^(st) mode (e.g., SPI mode). In thisembodiment, the resisters of the configurable output impedance may eachbe 50 Ohm resisters and the current sources I1 and I2 may be 6milliamps. V_(DD) may be a 2.5 volt source while the bias is a 1.2 voltsource. As shown in FIG. 9, the dashed line components are inactiveduring this mode and the solid line components are active. Accordinglythe solid line components provide a current steering amplifier that isproduced by switching transistors T1 and T7 on alternatively, per theinput signal 86, with enabling transistors T2 and T6 to steer thecurrents produced by the current sources I1 and I2 through the outputimpedance ladders to produce a differential amplified signal 90. Theoutput impedance ladder is biased via the bias voltage, which is coupledto the output impedance via transistors T5 and T10.

FIG. 10 is a schematic block diagram of the 10 module 62 and/or 72 inthe 2^(nd) mode of operation (e.g., HyperTransport mode). In thisexample, dashed lines illustrate the inactive components and the enablecomponents are illustrated by the solid line components. In operation,the alternating enabling, per the input signal 86, of transistors T3,T4, T8 and T9 provide a Class A or Class AB amplifier. The fourresisters of the configurable output impedance provide the outputimpedance.

By utilizing one of the various embodiments of a multi-functioninterface as a transmit input/output module within a multiple processordevice, the multiprocessor device may be configured within a processingsystem utilizing one or more communication protocols. In addition, themulti-function interface allows the multiprocessor device to beconfigured in a variety of ways. As one of average skill in the art willappreciate, other embodiments may be derived from the teaching of thepresent invention, without deviating from the scope of the claims.

What is claimed is:
 1. A multi-function interface comprising: digitalinterface module operably coupled to pass a first type of input signalwhen the multi-function interface is in a first mode and operablycoupled to pass a second type of input signal when the multi-functioninterface is in a second mode; configurable driver module operablycoupled to amplify the first type of input signal when themulti-function interface is in the first mode and to amplify the secondtype of input signal when the multi-function interface is in the secondmode; and configurable output impedance module operably coupled to theconfigurable driver module to provide a first output impedance when themulti-function interface is in the first mode and to provide a secondoutput impedance when the multi-function interface is in the secondmode.
 2. The multi-function interface of claim 1, wherein the digitalinterface module further comprises: first digital logic circuitryoperable to provide the first type of input signal to the configurabledriver when a control signal is of a first digital value; and seconddigital logic circuitry operable to provide the second type of inputsignal to the configurable driver when the control signal is of a seconddigital value.
 3. The multi-function interface of claim 1, wherein theconfigurable output impedance module further comprises: impedance ladderhaving a first end, a second end, and a tap, wherein the tap provides anoutput of the multi-function interface.
 4. The multi-function interfaceof claim 3, wherein the configurable driver module further comprises:first transistor having a gate, a drain, and a source, second transistorhaving a gate, a drain, and a source; bias circuit operably coupled toprovide a bias voltage to the first end of the impedance ladder; currentsource operably coupled to the source of the second transistor and to asupply return, wherein the drains of the first and second transistorsare operably coupled to the tap of the impedance ladder, wherein thesource of the first transistor is operably coupled to a supply source,wherein the gates of the first and second transistors are operablycoupled to receive the first type of input signal from the digitalinterface module when the multi-function interface is in the first mode.5. The multi-function interface of claim 3, wherein the configurabledriver module further comprises: first transistor having a gate, adrain, and a source; and second transistor having a gate, a drain, andsource, wherein the source of the first transistor is operably coupledto a supply voltage, wherein the drain of the first transistor isoperably coupled to the first end of the impedance ladder, wherein thedrain of the second transistor is operably coupled to the second end ofthe impedance ladder, wherein the source of the second transistor isoperably coupled to a supply return, and wherein the gates of the firstand second transistors are operably coupled to receive the second typeof input signal from the digital interface when the multi-functioninterface is in the second mode.
 6. The multi-function interface ofclaim 1, wherein the first type of input signal and the second type ofinput signal each further comprise a differential signal.
 7. Themulti-function interface of claim 6, wherein the digital interfacemodule further comprises: first digital logic circuitry operable toprovide a first leg of the first type of differential input signal tothe configurable driver when a control signal is of a first digitalvalue; second digital logic circuitry operable to provide a second legof the first type of differential input signal to the configurabledriver when the control signal is of the first digital value; thirddigital logic circuitry operable to provide the a first leg of thesecond type of differential input signal to the configurable driver whenthe control signal is of a second digital value; fourth digital logiccircuitry operable to provide the second leg of the second type ofdifferential input signal to the configurable driver when the controlsignal is of the second digital value.
 8. The multi-function interfaceof claim 7, wherein the configurable output impedance module furthercomprises: first impedance ladder having a first end, a second end, anda tap, wherein the tap of the first impedance ladder provides a firstleg of a differential output of the multi-function interface; and secondimpedance ladder having a first end, a second end, and a tap, whereinthe tap of the second impedance ladder provides a second leg of thedifferential output of the multi-function interface.
 9. Themulti-function interface of claim 8, wherein the configurable drivermodule further comprises: first transistor having a gate, a drain, and asource, second transistor having a gate, a drain, and a source; thirdtransistor having a gate, a drain, and a source; fourth transistorhaving a gate, a drain, and a source; bias circuit operably coupled toprovide a bias voltage to the first end of the first impedance ladderand to the first end of the second impedance ladder; current sourceoperably coupled to the sources of the second and fourth transistors andto a supply return, wherein the drains of the first and secondtransistors are operably coupled to the tap of the first impedanceladder, wherein the sources of the first and third transistors areoperably coupled to a supply source, wherein the drains of the third andfourth transistors are operably coupled to the tap of the secondimpedance ladder, wherein the gates of the first and second transistorsare operably coupled to receive a first leg of the first type ofdifferential input signal from the digital interface module when themulti-function interface is in the first mode, and wherein the gates ofthe third and fourth transistors are operably coupled to receive asecond leg of the first type of differential input signal from thedigital interface module when the multi-function interface is in thefirst mode.
 10. The multi-function interface of claim 8, wherein theconfigurable driver module further comprises: first transistor having agate, a drain, and a source; second transistor having a gate, a drain,and a source, wherein the source of the first transistor is operablycoupled to a supply voltage, wherein the drain of the first transistoris operably coupled to the first end of the first impedance ladder,wherein the drain of the second transistor is operably coupled to thesecond end of the first impedance ladder, wherein the source of thesecond transistor is operably coupled to a supply return, and whereinthe gates of the first and second transistors are operably coupled toreceive a first leg of the second type of differential input signal fromthe digital interface when the multi-function interface is in the secondmode; third transistor having a gate, a drain, and a source; and fourthtransistor having a gate, a drain, and a source, wherein the source ofthe third transistor is operably coupled to the supply voltage, whereinthe drain of the third transistor is operably coupled to the first endof the second impedance ladder, wherein the drain of the fourthtransistor is operably coupled to the second end of the second impedanceladder, wherein the source of the fourth transistor is operably coupledto the supply return, and wherein the gates of the third and fourthtransistors are operably coupled to receive a second leg of the secondtype of differential input signal from the digital interface when themulti-function interface is in the second mode.
 11. The multi-functioninterface of claim 1 further comprises: the first mode being inaccordance with a System Packet Interface (SPI) protocol; and the secondmode being in accordance with a HyperTransport (HT) protocol.
 12. Themulti-function interface of claim 11, wherein the configurable driverfurther comprises: being configured as a current steering driver whenthe multi-function interface is in the first mode; and being configuredas a class A amplifier or class AB amplifier when the multi-functioninterface is in the second mode.
 13. A multiple processor integratedcircuit comprises: a plurality of processing units; cache memory; memorycontroller operably coupled to system memory; internal bus operablycoupled to the plurality of processing units, the cache memory and thememory controller; packet manager operably coupled to the internal bus;node controller operably coupled to the internal bus; first configurablepacket-based interface; second configurable packet-based interface; andswitching module operably coupled to the packet manager, the nodecontroller, the first configurable packet-based interface, and thesecond configurable packet-based interface, wherein each of the firstand second configurable packet-based interfaces include a input/outputmodule and a media access control (MAC) layer module, wherein theinput/output module includes: digital interface module operably coupledto pass a first type of input signal when the multi-function interfaceis in a first mode and operably coupled to pass a second type of inputsignal when the multi-function interface is in a second mode;configurable driver module operably coupled to amplify the first type ofinput signal when the multi-function interface is in the first mode andto amplify the second type of input signal when the multi-functioninterface is in the second mode; and configurable output impedancemodule operably coupled to the configurable driver module to provide afirst output impedance when the multi-function interface is in the firstmode and to provide a second output impedance when the multi-functioninterface is in the second mode.
 14. The multiple processor integratedcircuit of claim 13, wherein the digital interface module furthercomprises: first digital logic circuitry operable to provide the firsttype of input signal to the configurable driver when a control signal isof a first digital value; and second digital logic circuitry operable toprovide the second type of input signal to the configurable driver whenthe control signal is of a second digital value.
 15. The multipleprocessor integrated circuit of claim 14, wherein the configurableoutput impedance module further comprises: impedance ladder having afirst end, a second end, and a tap, wherein the tap provides an outputof the multi-function interface.
 16. The multiple processor integratedcircuit of claim 15, wherein the configurable driver module furthercomprises: first transistor having a gate, a drain, and a source, secondtransistor having a gate, a drain, and a source; bias circuit operablycoupled to provide a bias voltage to the first end of the impedanceladder; current source operably coupled to the source of the secondtransistor and to a supply return, wherein the drains of the first andsecond transistors are operably coupled to the tap of the impedanceladder, wherein the source of the first transistor is operably coupledto a supply source, wherein the gates of the first and secondtransistors are operably coupled to receive the first type of inputsignal from the digital interface module when the multi-functioninterface is in the first mode.
 17. The multiple processor integratedcircuit of claim 15, wherein the configurable driver module furthercomprises: first transistor having a gate, a drain, and a source; andsecond transistor having a gate, a drain, and a source, wherein thesource of the first transistor is operably coupled to a supply voltage,wherein the drain of the first transistor is operably coupled to thefirst end of the impedance ladder, wherein the drain of the secondtransistor is operably coupled to the second end of the impedanceladder, wherein the source of the second transistor is operably coupledto a supply return, and wherein the gates of the first and secondtransistors are operably coupled to receive the second type of inputsignal from the digital interface when the multi-function interface isin the second mode.
 18. The multiple processor integrated circuit ofclaim 13, wherein the first type of input signal and the second type ofinput signal each further comprise a differential signal.
 19. Themultiple processor integrated circuit of claim 18, wherein the digitalinterface module further comprises: first digital logic circuitryoperable to provide a first leg of the first type of differential inputsignal to the configurable driver when a control signal is of a firstdigital value; second digital logic circuitry operable to provide asecond leg of the first type of differential input signal to theconfigurable driver when the control signal is of the first digitalvalue; third digital logic circuitry operable to provide the a first legof the second type of differential input signal to the configurabledriver when the control signal is of a second digital value; fourthdigital logic circuitry operable to provide the second leg of the secondtype of differential input signal to the configurable driver when thecontrol signal is of the second digital value.
 20. The multipleprocessor integrated circuit of claim 19, wherein the configurableoutput impedance module further comprises: first impedance ladder havinga first end, a second end, and a tap, wherein the tap of the firstimpedance ladder provides a first leg of a differential output of themulti-function interface; and second impedance ladder having a firstend, a second end, and a tap, wherein the tap of the second impedanceladder provides a second leg of the differential output of themulti-function interface.
 21. The multiple processor integrated circuitof claim 20, wherein the configurable driver module further comprises:first transistor having a gate, a drain, and a source, second transistorhaving a gate, a drain, and a source; third transistor having a gate, adrain, and a source; fourth transistor having a gate, a drain, and asource; bias circuit operably coupled to provide a bias voltage to thefirst end of the first impedance ladder and to the first end of thesecond impedance ladder; current source operably coupled to the sourcesof the second and fourth transistors and to a supply return, wherein thedrains of the first and second transistors are operably coupled to thetap of the first impedance ladder, wherein the sources of the first andthird transistors are operably coupled to a supply source, wherein thedrains of the third and fourth transistors are operably coupled to thetap of the second impedance ladder, wherein the gates of the first andsecond transistors are operably coupled to receive a first leg of thefirst type of differential input signal from the digital interfacemodule when the multi-function interface is in the first mode, andwherein the gates of the third and fourth transistors are operablycoupled to receive a second leg of the first type of differential inputsignal from the digital interface module when the multi-functioninterface is in the first mode.
 22. The multiple processor integratedcircuit of claim 20, wherein the configurable driver module furthercomprises: first transistor having a gate, a drain, and a source; secondtransistor having a gate, a drain, and a source, wherein the source ofthe first transistor is operably coupled to a supply voltage, whereinthe drain of the first transistor is operably coupled to the first endof the first impedance ladder, wherein the drain of the secondtransistor is operably coupled to the second end of the first impedanceladder, wherein the source of the second transistor is operably coupledto a supply return, and wherein the gates of the first and secondtransistors are operably coupled to receive a first leg of the secondtype of differential input signal from the digital interface when themulti-function interface is in the second mode; third transistor havinga gate, a drain, and a source; and fourth transistor having a gate, adrain, and a source, wherein the source of the third transistor isoperably coupled to the supply voltage, wherein the drain of the thirdtransistor is operably coupled to the first end of the second impedanceladder, wherein the drain of the fourth transistor is operably coupledto the second end of the second impedance ladder, wherein the source ofthe fourth transistor is operably coupled to the supply return, andwherein the gates of the third and fourth transistors are operablycoupled to receive a second leg of the second type of differential inputsignal from the digital interface when the multi-function interface isin the second mode.
 23. The multiple processor integrated circuit ofclaim 13 further comprises: the first mode being in accordance with aSystem Packet Interface (SPI) protocol; and the second mode being inaccordance with a HyperTransport (HT) protocol.
 24. The multipleprocessor integrated circuit of claim 23, wherein the configurabledriver further comprises: being configured as a current steering driverwhen the multi-function interface is in the first mode; and beingconfigured as a class A amplifier or class AB amplifier when themulti-function interface is in the second mode.
 25. A method forconfiguring a multi-function input/output interface, the methodcomprises: determining a digital value of a control signal; when thecontrol signal has a first digital value, passing a first type of inputsignal; driving the first type of input signal with a first impedancelevel to produce a first type of output drive; when the control signalhas a second digital value, passing a second type of input signal; anddriving the second type of input signal with a second impedance level toproduce a second type of output drive.
 26. The method of claim 25further comprises: the first digital value indicating that the firsttype of input signal is formatted in accordance with a System PacketInterface (SPI) protocol; and the second digital value indicating thatthe second type of input signal is formatted in accordance with aHyperTransport (HT) protocol.
 27. The method of claim 26 furthercomprises: current steering the first type of input signal to produce afirst type of output drive; and class A amplifying or class ABamplifying the second type of input signal to produce the second type ofoutput drive.
 28. An apparatus for configuring a multi-functioninput/output interface, the apparatus comprises: means for determining adigital value of a control signal; when the control signal has a firstdigital value, means for passing a first type of input signal; means fordriving the first type of input signal with a first impedance level toproduce a first type of output drive; when the control signal has asecond digital value, means for passing a second type of input signal;and means driving the second type of input signal with a secondimpedance level to produce a second type of output drive.
 29. Theapparatus of claim 28 further comprises: the first digital valueindicating that the first type of input signal is formatted inaccordance with a System Packet Interface (SPI) protocol; and the seconddigital value indicating that the second type of input signal isformatted in accordance with a HyperTransport (HT) protocol.
 30. Themethod of claim 26 further comprises: means for current steering thefirst type of input signal to produce a first type of output drive; andmeans for class A amplifying or class AB amplifying the second type ofinput signal to produce the second type of output drive.